Freescale Semiconductor, Inc.
Flash Memory
Flash EEPROM Registers
FEECTL — Flash EEPROM Control Register
$00F7
Bit 7
6
0
0
5
0
0
4
FEESWAI
0
3
SVFP
0
2
ERAS
0
1
LAT
0
Bit 0
ENPE
0
0
0
RESET:
This register controls the programming and erasure of the Flash
EEPROM.
FEESWAI — Flash EEPROM Stop in Wait Control
0 = Do not halt Flash EEPROM clock when the part is in wait mode.
1 = Halt Flash EEPROM clock when the part is in wait mode.
NOTE: The FEESWAI bit cannot be asserted if the interrupt vector resides in the
Flash EEPROM array.
SVFP — Status VFP Voltage
SVFP is a read only bit.
0 = Voltage of VFP pin is below normal programming voltage levels
1 = Voltage of VFP pin is above normal programming voltage levels
ERAS — Erase Control
This bit can be read anytime or written when ENPE = 0. When set, all
locations in the array will be erased at the same time. The boot block
will be erased only if BOOTP = 0. This bit also affects the result of
attempted array reads. See Table 7-1 for more information. Status of
ERAS cannot change if ENPE is set.
0 = Flash EEPROM configured for programming
1 = Flash EEPROM configured for erasure
LAT — Latch Control
This bit can be read anytime or written when ENPE = 0. When set, the
Flash EEPROM is configured for programming or erasure and, upon
the next valid write to the array, the address and data will be latched
for the programming sequence. See Table 7-1 for the effects of LAT
on array reads. A high voltage detect circuit on the VFP pin will prevent
assertion of the LAT bit when the programming voltage is at normal
levels.
MC68HC912DG128 — Rev 3.0
Technical Data
Flash Memory
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