Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM Registers
6.8 SIM Registers
The SIM has three memory mapped registers:
•
•
•
SIM break status register, SBSR
SIM reset status register, SRSR
SIM break flag control register, SBFCR
6.8.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
SBSW
See Note
0
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
R
= Reserved
Note: Writing a logic 0 clears SBSW.
Figure 6-17. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt.
0 = Stop mode or wait mode was not exited by break interrupt.
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it.
(See code example.) Writing 0 to the SBSW bit clears it.
;This code works if the H register has been pushed onto the stack in the break
;service routine software. This code should be executed at the end of the
;break service routine software.
HIBYTE
LOBYTE
;
EQU
EQU
5
6
If not SBSW, do RTI
BRCLR
SBSW, SBSR, RETURN
;See if wait mode or stop mode was exited
;by break.
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
TST
BNE
DEC
DEC
PULH
RTI
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN
;Restore H register.
MC68HC908RFRK2
MOTOROLA
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System Integration Module (SIM)
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