Freescale Semiconductor, Inc.
System Integration Module (SIM)
subsection of each module to see how each module is affected by the
break state.
6.6.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism — for example, a read of
one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the
flag as normal.
6.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
here. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
6.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral
clocks continues to run. Figure 6-12 shows the timing for wait mode
entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
Advance Information
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MC68HC908RFRK2
System Integration Module (SIM)
MOTOROLA
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