Freescale Semiconductor, Inc.
System Integration Module (SIM)
Low-Power Modes
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the mask
option register is logic 0, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 6-12. Wait Mode Entry Timing
Figure 6-13 and Figure 6-14 show the timing for WAIT recovery.
IAB
IDB
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
Figure 6-13. Wait Recovery from Interrupt or Break
32
CYCLES
32
CYCLES
IAB
$6E0B
$A6
RSTVCTH RSTVCTL
IDB $A6
RST
$A6
CGMXCLK
Figure 6-14. Wait Recovery from Internal Reset
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
95
System Integration Module (SIM)
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