Freescale Semiconductor, Inc.
Input/Output (I/O) Ports
13.4 Port B
Port B is a 4-bit special function port that shares two of its pins with the
timer (TIM) module and one with the buffered internal bus clock MCLK.
13.4.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the four
port B pins.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTB3
PTB2
PTB1
PTB0
Unaffected by reset
TCLK
Alternate
Functions:
TCH0
MCLK
= Unimplemented
Figure 13-5. Port B Data Register (PTB)
PTB[3:0] — Port B Data Bits
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
TCH0 — Timer Channel I/O Bit
The PTB2/TCH0 pin is the TIM channel 0 input capture/output
compare pin. The edge/level select bits, ELS0B:ELS0A, determine
whether the PTB2/TCH0 pin is a timer channel I/O or a general-
purpose I/O pin. See Section 15. Timer Interface Module (TIM).
TCLK — Timer Clock Bit
The PTB3/TCLK pin is the external clock input for TIM. The prescaler
select bits, PS[2:0], select PTB3/TCLK as the TIM clock input. (See
15.9.1 TIM Status and Control Register.) When not selected as the
TIM clock, PTB3/TCLK is available for general-purpose I/O.
Advance Information
180
MC68HC908RFRK2
Input/Output (I/O) Ports
MOTOROLA
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