Freescale Semiconductor, Inc.
Input/Output (I/O) Ports
Port B
MCLK — Bus Clock Bit
The bus clock (MCLK) is driven out of pin PTB0/MCLK when enabled
by the MCLKEN bit in port B data direction register bit 7.
13.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is
an input or an output. Writing a logic 1 to a DDRB bit enables the output
buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Address: $0005
Bit 7
MCLKEN
0
6
0
5
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
0
= Unimplemented
Figure 13-6. Data Direction Register B (DDRB)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTB0. If
MCLK is enabled, PTB0 is under the control of MCLKEN. Reset
clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRB[3:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[3:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
181
Input/Output (I/O) Ports
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