Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 11
DIGITAL TO ANALOG CONVERTER
This section describes Digital-to-Analog module used for DTMF generation.
11.1 DAC CONTROL AND DATA REGISTER
BIT 7
DACEN
0
BIT 6
0
BIT 5
DA5
0
BIT 4
DA4
0
BIT 3
DA3
0
BIT 2
DA2
0
BIT 1
DA1
0
BIT 0
DA0
0
DACDR
$000F
R
W
reset:
0
Figure 11-1. DAC Control and Data Register
DACEN - DAC Channel Enable
Ths read/write bit enables/disables the DAC module for DTMF output.
1 = Enable DAC module and con gure PA1/DTMF as DTMF output pin.
0 = Disable DAC module and con gure PA1/DTMF as general purpose
PA1 pin.
DA5-DA0
These bits determine the output voltage of the DAC channel. The output volt-
age value is determined by:
6
V
= (V x DA[0:5]) x 2
DD
OUT
There are 64 evenly spaced voltage levels available between V and V . The
DD
SS
lowest voltage is V and the highest voltage is 63/64V .
SS
DD
11.2 DAC OPERATION DURING WAIT MODE
In WAIT mode, the DAC continues to output a xed voltage level which is set by
the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if fur-
ther power saving is required in WAIT mode.
11.3 DAC OPERATION DURING STOP MODE
In STOP mode, the DAC continues to output a xed voltage level which is set by
the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if fur-
ther power saving is required in STOP mode.
MC68HC05PL4
REV 2.0
DIGITAL TO ANALOG CONVERTER
11-1
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