Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
April 30, 1998
10.5 8-BIT TIMER OPERATION DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If the
interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT
mode.
10.6 8-BIT TIMER OPERATION DURING STOP MODE
The timer ceases counting in STOP mode. When STOP is exited by an external
interrupt or an external reset, the internal oscillator will resume its operation, fol-
lowed by internal processor stabilization delay. The timer is then cleared to zero
and resumes its operation.
NOTE
The T8IF bit in T8CSR will be set after MCU exit from STOP mode. To avoid
generation of the timer 8 interrupt when exiting STOP mode, it is recommended to
clear T8IE bit prior entering STOP mode. After exiting STOP mode T8IF bit must
be cleared before setting T8IE bit.
8-BIT TIMER
MC68HC05PL4
REV 2.0
10-4
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