Freescale Semiconductor, Inc.
General Release Specification
Input/Output and Control Registers
2.5 Inp ut/ Outp ut a nd Control Re g iste rs
Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers
at locations $0000–$001F. Reading unimplemented bits will return
unknown states, and writing unimplemented bits will be ignored.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A Data Register
Port B Data Register
Port C Data Register
Port D Data Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port D Data Direction Register
Unimplemented
Unimplemented
SIOP Control Register
SIOP Status Register
SIOP Data Register
Reserved
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer Control Register
Timer Status Register
Input Capture MSB
Input Capture LSB
Output Compare MSB
Output Compare LSB
Timer MSB
Timer LSB
Alternate Counter MSB
Alternate Counter LSB
EPROM Programming Register
A/D Converter Data Register
A/D Converter Control & Status Reg
Reserved
Figure 2-2. MC68HC705P6A I/O and Control Registers Memory Map
MC68HC705P6A — Rev. 1.0
General Release Specification
Memory
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
