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68HC705P6A_1 参数 Datasheet PDF下载

68HC705P6A_1图片预览
型号: 68HC705P6A_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 134 页 / 3294 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Ge ne ra l De sc rip tion  
1.4.7 PD5 a nd PD7/ TCAP  
These two I/O pins comprise port D and one of them is shared with the  
16-bit timer subsystem. The state of PD5 is software programmable and  
is configured as an input during power-on or reset. PD7 is always an  
input. It may be read at any time, regardless of which mode of operation  
the 16-bit timer is in. Refer to Section 6. Input/Output Ports and  
Section 8. Capture/Compare Timer.  
1.4.8 TCMP  
This pin is the output from the 16-bit timer’s output compare function. It  
is low after reset. Refer to Section 8. Capture/Compare Timer.  
1.4.9 IRQ/ V (Ma ska b le Inte rrup t Re q ue st)  
PP  
This input pin drives the asynchronous interrupt function of the MCU in  
user mode and provides the V programming voltage in bootloader  
PP  
mode. The MCU will complete the current instruction being executed  
before it responds to the IRQ interrupt request. When the IRQ/V pin is  
PP  
driven low, the event is latched internally to signify an interrupt has been  
requested. When the MCU completes its current instruction, the interrupt  
latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit)  
in the condition code register is clear, the MCU will begin the interrupt  
sequence.  
Depending on the MOR LEVEL bit, the IRQ/V pin will trigger an  
PP  
interrupt on either a negative edge at the IRQ/V pin and/or while the  
PP  
IRQ/V pin is held in the low state. In either case, the IRQ/V pin must  
PP  
PP  
be held low for at least one t  
time period. If the edge- and level-  
ILIH  
sensitive mode is selected (LEVEL bit set), the IRQ/V input pin  
PP  
requires an external resistor connected to V for wired-OR operation.  
DD  
If the IRQ/V pin is not used, it must be tied to the V supply. The  
PP  
DD  
IRQ/V pin input circuitry contains an internal Schmitt trigger to improve  
PP  
noise immunity. Refer to Section 5. Interrupts.  
NOTE: If the voltage level applied to the IRQ/V pin exceeds V , it may affect  
PP  
DD  
the MCU’s mode of operation. See Section 3. Operating Modes.  
General Release Specification  
MC68HC705P6A Rev. 1.0  
General Description  
For More Information On This Product,  
Go to: www.freescale.com