Freescale Semiconductor, Inc.
General Description
Device Options
OSC1
OSC2
EXTERNAL
OSCILLATOR
+
COMP1
O
V
DD
-
INTERNAL
OSCILLATOR
C O NT R
T AR N S FE R
+
CURRENT
SOURCE
COMP2
-
÷2
16-BIT TIMER
(1) INPUT CAPTURE
(1) OUTPUT COMPARE
TCAP
TCMP
INT
V
COMPARATOR
CONTROL &
MULTIPLEXER
LVR
DD
TEMPERATURE
DIODE
ICF
OCF
TOF
15-STAGE
CORE TIMER
SYSTEM
V
SS
WATCHDOG &
ILLEGAL ADDR
DETECT
V
SS
PB0/AN0
PB1/AN1
PB2/AN2
V
SS
CPU CONTROL
CPU REGISTERS
ALU
INT
PB3/AN3/TCAP
PB4/AN4/TCMP/CMP1*
PB5/SDO
RESET
IRQ/V
68HC05 CPU
PP
ACCUM
PB6/SDI
INDEX REG
PB7/SCK
STK PTR
0 0 0 0 0 0 0 0 1 1
INT
SIMPLE SERIAL
INTERFACE
(SIOP)
PROGRAM COUNTER
COND CODE REG 1 1 1 H I N Z C
PA5*
PA4*
PA3*†
PA2*†
PA1*†
PA0*†
BOOT ROM — 240 BYTES
STATIC RAM (4T) — 224 BYTES
PC7*
PC6*
USER EPROM — 6160 BYTES
PC5*
PERSONALITY EPROM — 64 BITS
PORT C
PC4*
PC3*
PC2*
PC1*
PC0*
ONLY ON
28-PIN
VERSIONS
* High sink current capability
* High source current capability
† IRQ interrupt capability
Figure 1-1. User Mode Block Diagram
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
General Description
For More Information On This Product,
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FREESCALE [ Freescale ]
