Freescale Semiconductor, Inc.
Instruction Set
Opcode Map
Table 14-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
ff
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
Test Memory Byte for Negative or Zero
(M) – $00
— — ↕ ↕ —
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
A ← (X)
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr Operand (one or two bytes)
PC Program counter
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
Relative program counter offset byte
Relative program counter offset byte
SP Stack pointer
ff
H
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
X
Z
#
Index register
Zero flag
Immediate value
Logical AND
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
Logical OR
IMM Immediate addressing mode
INH Inherent addressing mode
Logical EXCLUSIVE OR
Contents of
( )
IX
IX1
IX2
M
N
n
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
–( ) Negation (two’s complement)
←
?
Loaded with
If
:
↕
—
Concatenated with
Set or cleared
Not affected
14.6 Op c od e Ma p
See Table 14-7.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Instruction Set
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