Freescale Semiconductor, Inc.
Instruction Set
Instruction Set Summary
Table 14-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
hh ll
ee ff
ff
JSR opr
DIR
EXT CD
IX2
IX1
IX
BD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
— — — — —
DD
ED
FD
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
X ← (M)
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — ↕ ↕ —
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
38
48
58
68
78
5
3
3
6
5
C
0
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
— — 0 ↕ ↕ INH
b7
b0
IX1
IX
ff
MUL
Unsigned Multiply
X : A ← (X) × (A)
0 — — — 0
INH
42
11
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
— — ↕ ↕ ↕ INH
IX1
IX
NOP
— — — — —
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
2
3
4
5
4
3
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
A ← (A) (M)
— — ↕ ↕ —
dd
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
39
49
59
69
79
5
3
3
6
5
C
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Instruction Set
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