Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
t
VDDR
V
DD
V
THRESHOLD (TYPICALLY 1-2 V)
DD
SC1PIN
4064 t
cyc
INTE RNAL
CLOCK
INTE RNAL
ADDRESS
BUS
1FFE
1FFE
1FFE
1FFE
1FFE
1FFE
1FFF
INTE RNAL
DATA
NEW
PCH
NEW
PCL
BUS
OTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. An internal POR reset is triggered as V rises through a threshold (typically 1-2 V).
DD
Figure 12-4. Power-On Reset Timing
NTERNAL
CLOCK
NTERNAL
DDRESS
BUS
1FFE
1FFE
1FFE
1FFE
1FFF
NEW PC
DUMMY
NEW PC
NTERNAL
DATA
NEW
PCH
NEW
PCL
OP
CODE
BUS
t
RL
RESET
OTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. The next rising edge of the internal processor clock after the rising edge of RESET initiates the reset sequence.
Figure 12-5. External Reset Timing
ELECTRICAL SPECIFICATIONS
MC68HC05P4A
Rev. 2.0
12-8
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