Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
1
OSC
t
RL
RESET
t
ILIH
2
IRQ
4064 t
cyc
3
IRQ
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
4
1FFE
1FFE
1FFE
1FFE
1FFE
1FFF
RESET OR INTERRUPT
VECTOR FETCH
NOTES:
1. Represents the internal clocking of the OSC1 pin.
2. IRQ pin edge–sensitive mask option.
3. IRQ pin level– and edge–sensitive mask option.
4. RESET vector address shown for timing example.
Figure 12-2. STOP Recovery Timing
Edge - Sensitive Trigger Condition
The minimum pulse width (t ) is
ILIH
t
IRQ (PIN)
ILIH
either 125ns (V = 5V) or 250ns
DD
(V = 3 V). The period t should
ILIL
t
DD
not be less thanthe number oft
ILIL
cyc
cycles it takes to execute the interrupt
service routine plus 19t cycles.
cyc
Level - Sensitive Trigger Condition
Ifafter servicinganinterruptthe IRQ
remains low, then the next interrupt is
recognized.
t
ILIH
IRQ1
•
•
•
NORMALLY
USED WITH
WIRE–ORed
CONNECTION
IRQn
RQ (MCU)
Figure 12-3. External Interrupt Timing
ELECTRICAL SPECIFICATIONS
Rev. 2.0
12-7
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