Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
11.3 Instruction Set Summary
Table 11-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
Table 11-6. Instruction Set Summary
Effect on
Source
Form
CCR
Operation
Description
M oed
C
H I N Z C
O
A
O
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
IMM A9 ii
DIR B9 dd
EXT C9 hh ll
2
3
4
5
4
3
Add with Carry
A ← (A) + (M) + (C)
↕ — ↕ ↕ ↕
IX2
IX1
IX
D9 ee ff
E9 ff
F9
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM AB ii
DIR BB dd
EXT CB hh ll
2
3
4
5
4
3
Add without Carry
Logical AND
A ← (A) + (M)
↕ — ↕ ↕ ↕
IX2
IX1
IX
DB ee ff
EB ff
FB
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM A4 ii
DIR B4 dd
EXT C4 hh ll
2
3
4
5
4
3
A ← (A) (M)
— — ↕ ↕ —
IX2
IX1
IX
D4 ee ff
E4 ff
F4
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
38 dd
48
58
68 ff
78
5
3
3
6
5
Arithmetic Shift Left
(Same as LSL)
— — ↕ ↕ ↕ INH
C
0
IX1
IX
b7
b7
b0
b0
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
37 dd
47
57
67 ff
77
5
3
3
6
5
C
Arithmetic Shift Right
— — ↕ ↕ ↕ INH
IX1
IX
Branch if Carry Bit
Clear
BCC rel
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
Branch if Carry Bit
Set (Same as BLO)
BCS rel
BEQ rel
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
— — — — — REL
— — — — — REL
25 rr
27 rr
3
3
Branch if Equal
INSTRUCTION SET
MC68HC05P4A
Rev. 2.0
11-8
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