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56F84462VLH 参数 Datasheet PDF下载

56F84462VLH图片预览
型号: 56F84462VLH
PDF下载: 下载PDF文件 查看货源
内容描述: MC56F844xx进展 [MC56F844xx Advance]
分类和应用:
文件页数/大小: 67 页 / 988 K
品牌: FREESCALE [ Freescale ]
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General  
Data1 Valid  
Data1  
Data2 Valid  
Data2  
Data3 Valid  
Data3  
Data  
Three-stated  
Data Invalid State  
Data Active  
Data Active  
Figure 4. Signal States  
7.3 Nonswitching electrical specifications  
7.3.1 Voltage and current operating requirements  
This section includes information about recommended operating conditions.  
NOTE  
Recommended VDD ramp rate is between 1 ms and 200 ms.  
Table 5. Recommended Operating Conditions (VREFLx = 0 V, VSSA = 0 V,  
VSS = 0 V)  
Characteristic  
Symbol  
VDD, VDDA  
VREFHA  
VREFHB  
VREFHC  
ΔVDD  
ΔVSS  
Notes1  
Min  
2.7  
3.0  
Typ  
Max  
3.6  
Unit  
V
Supply voltage2  
3.3  
ADC (Cyclic) Reference Voltage High  
VDDA  
V
ADC (SAR) Reference Voltage High  
Voltage difference VDD to VDDA  
Voltage difference VSS to VSSA  
Input Voltage High (digital inputs)  
Input Voltage Low (digital inputs)  
Oscillator Input Voltage High  
2.0  
-0.1  
-0.1  
VDDA  
0.1  
V
V
V
V
V
V
0
0
0.1  
VIH  
Pin Groups 1, 2 0.7 x VDD  
Pin Groups 1, 2  
5.5  
VIL  
0.35 x VDD  
VDD + 0.3  
VIHOSC  
Pin Group 4  
2.0  
XTAL driven by an external clock source  
Oscillator Input Voltage Low  
Output Source Current High (at VOH min.)3  
• Programmed for low drive strength  
VILOSC  
IOH  
Pin Group 4  
-0.3  
0.8  
V
Pin Group 1  
Pin Group 1  
-2  
-9  
mA  
• Programmed for high drive strength  
Output Source Current Low (at VOL max.)3  
• Programmed for low drive strength  
IOL  
Pin Groups 1, 2  
Pin Groups 1, 2  
2
9
mA  
• Programmed for high drive strength  
1. Default Mode  
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK  
• Pin Group 2: RESET, GPIOA7  
• Pin Group 3: ADC and Comparator Analog Inputs  
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.  
26  
Freescale Semiconductor, Inc.  
Preliminary  
General Business Information