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56F84567VLL 参数 Datasheet PDF下载

56F84567VLL图片预览
型号: 56F84567VLL
PDF下载: 下载PDF文件 查看货源
内容描述: MC56F8458x进展 [MC56F8458x Advance]
分类和应用:
文件页数/大小: 68 页 / 1019 K
品牌: FREESCALE [ Freescale ]
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Peripheral highlights  
• Each complementary pair can operate with its own PWM frequency base and  
deadtime values  
• 4 time base in each PWM module  
• Independent top and bottom deadtime insertion for each complementary pair  
• PWM outputs can operate as complementary pairs or independent channels  
• Independent control of both edges of each PWM output  
• Enhanced input capture and output compare functionality on each input  
• Channels not used for PWM generation can be used for buffered output compare  
functions  
• Channels not used for PWM generation can be used for input capture functions  
• Enhanced dual edge capture functionality  
• Synchronization to external hardware or other PWM supported  
• Double buffered PWM registers  
• Integral reload rates from 1 to 16  
• Half-cycle reload capability  
• Multiple output trigger events can be generated per PWM cycle via hardware  
• Support for double switching PWM outputs  
• Up to eight fault inputs can be assigned to control multiple PWM outputs  
• Programmable filters for fault inputs  
• Independently programmable PWM output polarity  
• Individual software control of each PWM output  
• All outputs can be programmed to change simultaneously via a FORCE_OUT event  
• PWMX pin can optionally output a third PWM signal from each submodule  
• Option to supply the source for each complementary PWM signal pair from any of  
the following:  
• Crossbar module outputs  
• External ADC input, taking into account values set in ADC high and low limit  
registers  
1.6.2 12-bit Analog-to-Digital Converter (Cyclic type)  
• Two independent 12-bit analog-to-digital converters (ADCs)  
• 2 x 8-channel external inputs  
• Built-in x1, x2, x4 programmable gain pre-amplifier  
• Maximum ADC clock frequency is up to 20 MHz with 50 ns period  
• Single conversion time of 8.5 ADC clock cycles  
• Additional conversion time of 6 ADC clock cycles  
• Sequential, parallel, and independent scan mode  
• First 8 samples have offset, limit and zero-crossing calculation supported  
• ADC conversions can be synchronized by any module connected to internal crossbar  
module, such as PWM and timer modules and GPIO and comparators  
MC56F8458x Advance Information Data Sheet, Rev. 2, 06/2012.  
8
Freescale Semiconductor, Inc.  
Preliminary  
General Business Information  
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