Overview
Table 1. 56F844x/5x/7x Family (continued)
Part
Number
Standard
channels
PWMB
with input
capture:
Standard
channels
DAC
Quad
Decoder
DMA
CMP
QSCI
QSPI
I2C/SMBus
FlexCAN
LQFP
package
pin count
MC56F84
789
4
786
1
769
4
766
1
763
1
553
1
550
0
543
1
540
0
587
2x
12
0
585
1x
12,
1x9
0
567
2x
12
0
565
1x
12,
1x9
0
462
1x9
452
1x9
451
1x6
442
1x9
441
1x6
1x
12
1x7
1x
12
1x7
0
0
0
0
0
0
0
0
0
0
1
1
Yes
4
3
3
2
1
100
1
1
Yes
4
3
2
2
1
80
1
1
Yes
4
3
3
2
1
100
1
1
Yes
4
3
2
2
1
80
1
0
Yes
4
2
2
2
1
64
1
0
Yes
4
2
2
2
1
64
1
0
Yes
3
2
2
2
1
48
1
0
Yes
4
2
2
2
1
64
1
0
Yes
3
2
2
2
1
48
1
1
Yes
4
3
3
2
1
100
1
1
Yes
4
3
2
2
1
80
0
1
Yes
4
3
3
2
1
100
0
1
Yes
4
3
2
2
1
80
1
1
Yes
4
2
2
2
1
64
0
1
Yes
4
2
2
2
1
64
0
1
Yes
3
2
2
2
1
48
0
1
Yes
4
2
2
2
0
64
0
1
Yes
3
2
2
2
0
48
1. This total assumes no FlexNVM is used with FlexRAM for EEPROM.
1.2 56800EX 32-bit Digital Signal Controller Core
• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual
Harvard architecture
• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
• Support for concurrent instruction fetches in the same cycle and dual data
accesses in the same cycle
• 20 addressing modes
• As many as 80 million instructions per second (MIPS) at 80 MHz core frequency
• 162 basic instructions
• Instruction set supports both fractional arithmetic and integer arithmetic
• 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement,
addition, subtraction, and logical operation
• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
MC56F8458x Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
Preliminary
General Business Information
5
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
