Configuration
8.3 Configuration
There are six GPIO ports defined on the 56F8367/56F8167. The width of each port and the associated
peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is
shown in Table 8-3.
Table 8-1 56F8367 GPIO Ports Configuration
Available
Pins in
56F8367
GPIO
Port
Port
Width
Peripheral Function
Reset Function
A
B
C
14
8
14
8
14 pins - EMI Address pins
EMI Address
EMI Address
8 pins - EMI Address pins
11
11
4 pins -DEC1 / TMRB / SPI1
4 pins -DEC0 / TMRA
DEC1 / TMRB
DEC0 / TMRA
3 pins -PWMA current sense
PWMA current sense
D
E
13
14
13
14
6 pins - EMI CSn
2 pins - SCI1
2 pins - EMI CSn
3 pins -PWMB current sense
EMI Chip Selects
SCI1
EMI Chip Selects
PWMB current sense
SCI0
2 pins - SCI0
EMI Address
SPI0
2 pins - EMI Address pins
4 pins - SPI0
TMRC
2 pins - TMRC
TMRD
4 pins - TMRD
F
16
16
16 pins - EMI Data
EMI Data
Table 8-2 56F8167 GPIO Ports Configuration
Available
Pins in
56F8167
GPIO
Port
Port
Width
Peripheral Function
Reset Function
14 pins - EMI Address pins
A
B
C
14
8
14
8
EMI Address
EMI Address
8 pins - EMI Address pins
4 pins - SPI1
11
11
SPI1
4 pins - DEC0 / TMRA
3 pins - Dedicated GPIO
DEC0 / TMRA
GPIO
6 pins - EMI CSn
2 pins - SCI1
D
13
13
EMI Chip Selects
SCI1
2 pins - EMI CSn
3 pins -PWMB current sense
EMI Chip Selects
PWMB current sense
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
133
FREESCALE [ Freescale ]
