10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Typical
Min
Typical
Max
Characteristic
Symbol
Unit
See Figure
10-5
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—
21
ns
Minimum RESET Assertion Duration
tRA
tRDA
16T
63T
1.5T
18T
14T
18T
14T
22T
18T
22T
18T
1.5T
—
64T
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10-5
10-5
10-6
10-7
RESET Deassertion to First External Address Output3
Edge-sensitive Interrupt Request Width
tIRW
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
tIDM - FAST
tIG
tIG - FAST
tIRI
tIRI -FAST
tIF
tIF - FAST
tIW
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
ns
ns
ns
ns
10-7
10-8
10-9
10-9
Delay from IRQA Assertion (exiting Wait) to External
Data Memory Access4
Delay from IRQA Assertion to External Data Memory
Access (exiting Stop)
IRQA Width Assertion to Recover from Stop State5
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
21
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2 T.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This
is not the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
RESET
tRA
tRAZ
tRDA
First Fetch
A0–A15,
D0–D15
Figure 10-5 Asynchronous Reset Timing
56F8366 Technical Data, Rev. 6
156
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
