1
Table 4-5 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
PWMB
PWMA
PWMB
PWMA
core
77
78
79
80
81
0-2
0-2
0-2
0-2
- 1
P:$9A
P:$9C
P:$9E
P:$A0
P:$A2
Reload PWM B
Reload PWM A
PWM B Fault
PWM A Fault
SW Interrupt LP
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are
the chip reset addresses; therefore, these locations are not interrupt vectors.
2.
4.4 Data Map
Note: Data Flash is NOT available on the 56F8155 device.
1, 2
Table 4-6 Data Memory Map
Begin/End
Address
EX = 03
EX = 14
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory
External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 3000
External Memory
X:$00 2FFF
X:$00 2000
On-Chip Data Flash
8KB
External Memory
X:$00 1FFF
X:$00 0000
On-Chip Data RAM
16KB5
1. Information in shaded areas not applicable to 56F8355/56F8155.
2. All addresses are 16-bit Word addresses, not byte addresses.
3. In the Operating Mode Register.
56F8355 Technical Data, Rev. 12
42
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
