Peripheral Memory Mapped Registers
Table 4-8 EOnCE Memory Map (Continued)
Address
Register Acronym
Register Name
Reserved
X:$FF FFFC
X:$FF FFFD
X:$FF FFFE
X:$FF FFFF
OCLSR (8 bits)
Core Lock / Unlock Status Register
OTXRXSR (8 bits)
OTX / ORX (32 bits)
OTX1 / ORX1
Transmit and Receive Status and Control Register
Transmit Register / Receive Register
Transmit Register Upper Word
Receive Register Upper Word
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-9 summarizes base addresses for the set of peripherals on the 56F8355 and 56F8155 devices.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Note: Features in italics are NOT available in the 56F8155 device.
Table 4-9 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
External Memory Interface
Timer A
EMI
X:$00 F020
X:$00 F040
X:$00 F080
X:$00 F0C0
X:$00 F100
X:$00 F140
X:$00 F160
X:$00 F180
X:$00 F190
X:$00 F1A0
X:$00 F200
X:$00 F240
X:$00 F270
X:$00 F280
X:$00 F290
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
TMRA
TMRB
TMRC
TMRD
PWMA
PWMB
DEC0
DEC1
ITCN
Timer B
Timer C
Timer D
PWM A
PWM B
Quadrature Decoder 0
Quadrature Decoder 1
ITCN
ADC A
ADCA
ADCB
ADC B
Temperature Sensor
SCI #0
TSENSOR
SCI0
SCI #1
SCI1
56F8355 Technical Data, Rev. 12
Freescale Semiconductor
Preliminary
45
FREESCALE [ Freescale ]
