Interrupt Vector Table
7. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must have
its own mass erase.
4.3 Interrupt Vector Table
Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part
5.6.11 for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Note: PWMA, FlexCAN, Quadrature Decoder1, and Quad Timers B and D are NOT available on the
56F8155 device.
1
Table 4-5 Interrupt Vector Table Contents
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
Reserved for Reset Overlay2
Reserved for COP Reset Overlay2
Illegal Instruction
SW Interrupt 3
core
core
core
core
core
core
2
3
4
5
6
7
3
3
P:$04
P:$06
P:$08
P:$0A
P:$0C
P:$0E
3
HW Stack Overflow
Misaligned Long Word Access
OnCE Step Counter
OnCE Breakpoint Unit 0
Reserved
3
1-3
1-3
core
core
core
9
1-3
1-3
1-3
P:$12
P:$14
P:$16
OnCE Trace Buffer
OnCE Transmit Register Empty
OnCE Receive Register Full
Reserved
10
11
core
core
core
core
core
14
15
16
17
18
2
1
P:$1C
P:$1E
P:$20
P:$22
P:$24
SW Interrupt 2
SW Interrupt 1
0
SW Interrupt 0
0-2
0-2
IRQA
IRQB
56F8355 Technical Data, Rev. 12
Freescale Semiconductor
Preliminary
39
FREESCALE [ Freescale ]
