Architecture Block Diagram
To/From IPBus Bridge
TA0o on Figure 1-6 (PWM)
TA0 on Figure 1-6 (GPIOA6)
TA0 on Figure 1-4 (GPIOB4)
T0o
T0i
TA1 on Figure 1-4(GPIOA12)
T1o
T1i
TA1 on Figure 1-6 (GPIOB5)
CMPAO on Figure 1-6 (CMPA)
SYNC1 on Figure 1-3 (ADC)
TA2o on Figure 1-6 (PWM)
TA2 on Figure 1-6 (GPIOA4)
TMRA
T2o
T2i
TA2 on Figure 1-5 (GPIOA8)
TA2 on Figure 1-4 (GPIOA13)
TA2 on Figure 1-4 (GPIOB2)
CMPBO on Figure 1-6 (CMPB)
SYNC0 on Figure 1-3 (ADC)
TA3o on Figure 1-6 (PWM)
TA3 on Figure 1-6 (GPIOA5)
T3o
T3i
TA3 on Figure 1-5 (GPIOA9)
TA3 on Figure 1-4 (GPIOA14)
TA 3 on Figure 1-4 (GPIOB3)
RELOAD on Figure 1-6 (PWM)
IPBus
Figure 1-7 56F8037 I/O Pin-Out Muxing (Part 5/5)
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
15
FREESCALE [ Freescale ]
