Architecture Block Diagram
To/From IPBus Bridge
IPBus
INTC
SYNC
MSTR_CNT_EN
PIT0
3
DAC SYNC on Figure 1-5
MSTR_CNT_EN
SYNC
SYNC
PIT1
MSTR_CNT_EN
PIT2
2
3
SYNC0, SYNC1 on Figure 1-7
LIMIT on Figure 1-6
Sync0, Over/Under
ANA0
ANA0 on Figure 1-5
Sync1
Limits
GPIOC2
GPIOC3
ANA2 (VREFHA
)
)
ANA3 (VREFLA
ANA4 on Figure 1-4
ANA4
GPIOC1, 9-11
ANA1, 5-7
4
ANA1, 5-7
ADC
ANB0
ANB0 on Figure 1-5
GPIOC6
GPIOC7
ANB2 (VREFHA
)
)
ANB3 (VREFLB
ANB4 on Figure 1-4
ANB4
GPIOC5, 13-15
ANB1, 5-7
4
ANB1, 5-7
Figure 1-3 56F8037 I/O Pin-Out Muxing (Part 1/5)
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
11
FREESCALE [ Freescale ]
