Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8037 are organized into functional groups, as detailed in Table 2-1.
Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present
on a pin, sorted by pin number.
Table 2-1 Functional Group Pin Allocations
Functional Group
Power Inputs (VDD, VDDA
Number of Pins
)
4
5
Ground (VSS, VSSA
Supply Capacitors
Reset1
)
2
1
Pulse Width Modulator (PWM) Ports1
Queued Serial Peripheral Interface 0 (QSPI0) Ports1
Queued Serial Peripheral Interface 1 (QSPI1) Ports1
Timer Module A (TMRA) Ports1
13
4
4
4
Timer Module B (TMRB) Ports1
4
Analog-to-Digital Converter (ADC) Ports1
Digital-to-Analog Converter (DAC) Ports1
Queued Serial Communications Interface 0 (QSCI0) Ports1
Queued Serial Communications Interface 1 (QSCI1) Ports1
Inter-Integrated Circuit Interface (I2C) Ports1
MSCAN Ports1
16
2
2
2
2
2
Oscillator Signals1
2
JTAG/Enhanced On-Chip Emulation (EOnCE)1
4
1. Pins may be shared with other peripherals. See Table 2-2.
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
17
FREESCALE [ Freescale ]
