56F8014 General Description
2
• Up to 32 MIPS at 32MHz core frequency
• One Inter-Integrated Circuit (I C) Port
• DSP and MCU functionality in a unified,
C-efficient architecture
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• 16KB Program Flash
• Integrated Power-On Reset and Low-Voltage Interrupt
Module
• 4KB Unified Data/Program RAM
• One 5-channel PWM module
• Two 4-channel 12-bit ADCs
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
• One Serial Communication Interface (SCI) with LIN
slave functionality
• One Serial Peripheral Interface (SPI)
• One 16-bit Quad Timer
V
V
V
V
V
SSA
CAP
DD
SS_IO
DDA
RESET
4
2
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Low-Voltage
Supervisor
Analog Reg
PWM
or Timer Port
or GPIOA
5
PWM Outputs
16-Bit
56800E Core
Data ALU
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Bit
Manipulation
Unit
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
PAB
PDB
CDBR
CDBW
4
4
AD0
AD1
ADC
or
GPIOC
Memory
R/W Control
XDB2
XAB1
XAB2
Program Memory
8K x 16 Flash
System Bus
Control
PAB
Unified Data /
Program RAM
4KB
PDB
CDBR
CDBW
IPBus Bridge (IPBB)
Timer or
GPIOB
2
2
SCI
P
O
R
System
Integration
Module
SPI or I C
Interrupt
Controller
COP/
Watchdog
2
O
S
C
Clock
Generator*
or I C
or GPIOB
or Timer
or GPIOB
*Includes On-Chip
Relaxation Oscillator
4
2
56F8014 Block Diagram
56F8014 Technical Data, Rev. 9
4
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
