Electrical Design Considerations
Part 14 Appendix
Register acronyms are revised from previous device data sheets to provide a cleaner register description.
A cross reference to legacy and revised acronyms are provided in the following table.
Peripheral Reference Manual
Data Sheet
Memory Address
Start End
Processor
Expert
Acronym
Legacy
New Acronym
Module
Register Name
New Acronym
Legacy Acronym
Acronym
ADC Control Register 1
CTRL1
CTRL2
ZXCTRL
CLIST1
CLIST2
SDIS
ADCR1
ADCR2
ADC_CTRL1
ADC_CTRL2
ADC_ZXCTRL
ADC_CLIST1
ADC_CLIST2
ADC_SDIS
ADC_ADCR1
ADC_ADCR2
ADC_ADCR1
ADC_ADCR2
0xF080
Control Register 2
0xF081
0xF082
Zero Crossing Control Register
ADZCC
ADC_ADZCC
ADC_ADZCC
Channel List Register 1
Channel List Register 2
Sample Disable Register
Status Register
ADLST1
ADC_ADLST1
ADC_ADLST2
ADC_ADSDIS
ADC_ADLST1
ADC_ADLST2
ADC_ADSDIS
ADC_ADSTAT
ADC_ADLSTAT
ADC_ADZCSTAT
ADC_ADRSLT0-7
ADC_ADLLMT0-7
0xF083
ADLST2
0xF084
ADSDIS
0xF085
STAT
ADSTAT
ADC_STAT
ADC_ADSTAT
ADC_ADLSTAT
ADC_ADZCSTAT
ADC_ADRSLT0-7
ADC_ADLLMT0-7
ADC_ADHLMT0-7
ADC_ADOFS0-7
ADC_ADPOWER
ADC_ADCAL
0xF086
Limit Status Register
LIMSTAT
ZXSTAT
RSLT0-7
LOLIM0-7
HILIM0-7
OFFST0-7
PWR
ADLSTAT
ADZCSTAT
ADRSLT0-7
ADLLMT0-7
ADHLMT0-7
ADOFS0-7
ADPOWER
ADCAL
ADC_LIMSTAT
ADC_ZXSTAT
ADC_RSLT0-7
ADC_LOLIM0-7
ADC_HILIM0-7
ADC_OFFST0-7
ADC_PWR
0xF087
Zero Crossing Status Register
Result Registers 0-7
0xF088
0xF089 0XF090
0XF091 0XF098
Low Limit Registers 0-7
High Limit Registers 0-7
Offset Registers 0-7
ADC_ADHLMT0-7 0XF099 0XF0A0
ADC_ADOFS0-7
ADC_ADPOWER
ADC_CAL
0XF0A1 0XF0A8
0XF0A9
Power Control Register
Voltage Reference Register
CAL
ADC_VREF
0XF0AA
COP Control Register
CTRL
TOUT
CNTR
COPCTL
COPTO
COP_CTRL
COP_TOUT
COP_CNTR
COPCTL
COPTO
COPCTL
COPTO
0XF0E0
0XF0E1
0XF0E2
Time-Out Register
Counter Register
COPCTR
COPCTR
COPCTR
2
Address Register
ADDR
FDIV
IBAD
IBFD
IBCR
IBSR
IBDR
IBNR
I2C_ADDR
I2C_FDIV
I2C_CTRL
I2C_STAT
I2C_DATA
I2C_NFILT
I2C_IBAD
I2C_IBFD
I2C_IBCR
I2C_IBSR
I2C_IBDR
I2C_IBNR
IBAD
IBFD
IBCR
IBSR
IBDR
IBNR
0xF0D0
0xF0D1
0xF0D2
0xF0D3
0xF0D4
0xF0D5
I C
Frequency Divider Register
Control Register
CTRL
STAT
DATA
NFILT
Status Register
Data I./O Register
Noise Filter Register
ITCN Interrupt Priority Register 0-4
Vector Base Address Register
Fast Interrupt Match 0 Register
Fast Interrupt Vector Address Low 0
Fast Interrupt Vector Address High 0
Fast Interrupt Match 1 Register
Fast Interrupt Vector Address Low 1
Fast Interrupt Vector Address High 1
Interrupt Pending Register 0
Interrupt Pending Register 1
Interrupt Pending Register 2
Interrupt Control Register
N/A
N/A
N/A
N/A
ITCN_IPR0-4
ITCN_VBA
ITCN_IPR0-4
ITCN_VBA
ITCN_FIM0
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
ITCN_ICTL
PLLCR
INTC_IPR0-4
INTC_VBA
INTC_FIM0
INTC_FIVAL0
INTC_FIVAH0
INTC_FIM1
INTC_FIVAL1
INTC_FIVAH1
INTC_IRQP0
INTC_IRQP1
INTC_IRQP2
INTC_ICTL
PLLCR
0XF060 0XF064
0XF065
0XF066
0XF067
0XF068
0xF069
N/A
N/A
ITCN_FIM0
N/A
N/A
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
N/A
N/A
N/A
N/A
N/A
N/A
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
ITCN_ICTRL
OCCS_CTRL
OCCS_DIVBY
OCCS_STAT
OCCS_SHUTDN
OCCS_OCTRL
0xF06A
0xF06B
0xF06C
0xF06D
0xF06E
0xF072
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
OCCS Control Register
CTRL
DIVBY
STAT
SHUTDN
OCTRL
PLLCR
PLLDB
PLLSR
SHUTDOWN
OSCTL
0xF0F0
0xF0F1
0xF0F2
0xF0F4
0xF0F5
Divide-By Register
PLLDB
PLLDB
Status Register
PLLSR
PLLSR
Shutdown Register
SHUTDOWN
OSCTL
SHUTDOWN
OSCTL
Oscillator Control Register
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
119
FREESCALE [ Freescale ]
