FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
longer than the delay period of tDELAY and VVB+ is still less
DC MOTOR DRIVE SYSTEM
than VVB+T . In this situation RESET will remain low until VVB+
-
This drive circuitry provides bi-directional drive to a DC
motor via two inputs, DCM_PWM (an external pin, CMOS-
compatible input) and DRx_DIR_DCM (a bit in the serial input
port; refer to Tables 7 through 9, pp. 15–17). This drive is
powered from VB+. The DC motor control circuitry uses
voltage mode control.
is greater than VVB+T-, at which point RESET will be released
immediately and there will be no delay period. If VVB+ passes
through VVB+T+ during the tDELAY period, RESET will remain
low until the end of the tDELAY period, which started at the time
VV1_FB passed through the VV1T+ level.
To drive a DC motor the 34920 outputs DR2A1 and
DR2A2 must be connected together externally, then
connected to the DC motor “+” lead. Likewise, the 34920
outputs DR2B1 and DR2B2 must be connected together
externally, then connected to the DC motor “-“ lead (see
Figure 8).
During power-down this output immediately asserts a logic
low at the point when VV1_FB drops down to the trip point of
VV1T . Also, if VVB+ drops below VVB+T and VV1_FB is still at
-
-
or above VV1T-, RESET will be pulled low.
RESET BEHAVIOR
This drive provides internal overtemperature sensing for
protection. During an overtemperature event, when the
device TJ is at or above TJ(SHUTDOWN), the internal thermal
The following conditions describe the behavior of the
RESET circuit.
protection circuit disables the drive outputs by driving both
outputs to the high state until the device temperatures have
dropped below the lower thermal threshold temperature
A Note on Terminology Assertion of RESET is defined
as the RESET pin outputting a logic low voltage, and de-
assertion is when the pin is pulled up to the VCC voltage.
TJ(ENABLE), at which time the drive is re-enabled.
On the power-up condition, RESET behaves as follows:
• If 1.0 V < VV1_FB < VV1T+ or VVB+ < VVB+T+, RESET will
The crossover delay must be controlled to provide
sufficient time for cross-condition suppression. At no time can
both the upper and lower output devices on the same side of
the H-bridge be allowed to conduct simultaneously. Also,
following a turn-on event a blanking period is included to
prevent false turn-offs owing to the initial turn-on current
spike, which results from motor circuit capacitance.
be asserted.
Important If VV1_FB < 1.0 V, RESET is undefined.
• If RESET is asserted owing to VV1_FB < VV1T , then
-
when VV1_FB rises monotonically from below VV1T to
-
above VV1T+, RESET will de-assert after a duration of
Note During power-on the DC Motor Driver circuit inhibits
its outputs when VVB+ is at 4.0 V or greater until RESET is
tDELAY
.
• If RESET is asserted owing to VVB+ < VVB+T+ and
released. Likewise, during power-down of the machine the
DC Motor Driver circuit inhibits its outputs from the point
when RESET goes low until VVB+ has dropped below 4.0 V.
VV1_FB ≥ VV1T+, then when VVB+ rises to the VVB+T+
level RESET will de-assert with no delay. The only case
where a delay would be seen is if the time period from
where VV1_FB rises to the VV1T+ level to the point where
RESET FUNCTIONALITY
VVB+ rises to the VVB+T+ level is less than the tDELAY
The 34920 provides an output, RESET, that drives an
external reset signal to the system microprocessor and/or the
system digital logic IC. This signal is an active low logic level
signal that is derived by monitoring the level of the VCC pin.
period. Then the delay in de-asserting RESET would be
the remaining tDELAY time, thereby maintaining the full
t
DELAY period, between the time when VV1_FB reaches
VV1T+ and the de-assertion of RESET, that is required
for a reliable system reset.
This output is the equivalent of an open drain- (or open
collector-) type output, with an internal 2.5 kΩ pull-up to VCC
.
This output pin can be driven by other external sources and
therefore the state of RESET must be monitored by the
34920.
On the power-down condition, RESET behaves as follows:
• If RESET is not asserted, and the VV1_FB voltage
monotonically decreases to a value below the negative-
Note When RESET is asserted either internally or from an
external source, all 34920 motor drive outputs will be in their
inactive states, and the serial input port will be loaded with the
“Reset Value” (refer to Tables 6 through 9). The V2 voltage
regulator will be enabled.
going threshold of VV1T and remains below VV1T for
-
-
longer than tPERSIST (10 µs to 30 µs), RESET will be
asserted. RESET will remain asserted while 1.0 V <
VV1_FB < VV1T+. If VV1_FB falls below 1.0 V, the RESET
signal is undefined.
During power-up this output asserts a logic low level, and
it monitors the V1 regulator output voltage and detects the
point that it reaches VV1T+. The output will then remain low
•
RESET will also be asserted when VVB+ decreases
below the VVB+T+ level. This will occur even if the
VV1_FB level is still above VV1T
.
-
for a delay of 15 ms to 50 ms before releasing to a high state.
A second case is if VV1_FB is at or above VV1T+ for a period
34920
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
FREESCALE [ Freescale ]
