FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
DR2PWM DR2_MODE
VB+
34920
DR2
DR2A1
DR2B1
+
-
Phase A H-Bridge
SDR2_DIR_PH A
SDR2_CURR_I1 PHASEA
SDR2_CURR_I0 PHASEA
DC
Motor
DR2_DIR_DCM
DR2A2
DR2B2
Phase B H-Bridge
SDR2_DIR_PH_B
SDR2_CURR_I1_PHASEB
SDR2_CURR_I0_PHASEB
Figure 8. Simplified DC Application Diagram Showing 1 of 2 Motor Drive Circuits
no time will both the upper and lower output device on the
same side of the H-bridge be allowed to conduct
simultaneously. Also, following a turn-on event a blanking
period is included to prevent false turn-offs owing to the initial
turn-on current spike, which results from motor circuit
capacitance.
BIPOLAR CURRENT REGULATED STEP MOTOR
DRIVE SYSTEM
The drive circuitry is powered by the VVB+ supply voltage.
For example, with external current sense resistors of 0.910 Ω
±1%, the drive circuitry provides drive for a bipolar step motor
at current levels of approximately 183 mA, 367 mA, and
550 mA. Current mode operation supports quarter stepping.
This drive has internal overtemperature sensing for
protection. During an overtemperature event, when the
This drive enters the fast current decay mode when both
the CURR_I0_PHASEX and CURR_I1_PHASEX inputs are
set to the logic [1] level. In fast current decay mode, any
residual motor winding current is forced into the VVB+ supply
device TJ is at or above TJ(SHUTDOWN), the internal thermal
protection circuit disables the drive outputs by driving all
outputs to the zero current state until the device temperatures
have dropped below the lower thermal threshold temperature
rail when going to a zero current state from a non-zero
current level. This forces the motor winding current toward
zero as quickly as possible.
T
J(ENABLE), at which time the driver is re-enabled.
Note During power-on the step motor driver circuit inhibits
its outputs when VVB+ is at 4.0 V or greater until RESET is
For each of the two H-bridge drivers, controlled crossover
delay, a blanking period, and internal overtemperature
sensing are provided. The crossover delay is controlled to
provide sufficient time for cross-conduction suppression. At
released. Likewise, during power-down the step motor driver
circuit inhibits its outputs from the point when RESET goes
low until VVB+ has dropped below 4.0 V.
34920
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FREESCALE [ Freescale ]
