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34701 参数 Datasheet PDF下载

34701图片预览
型号: 34701
PDF下载: 下载PDF文件 查看货源
内容描述: 1.5 A开关模式电源与线性稳压器 [1.5 A Switch-Mode Power Supply with Linear Regulator]
分类和应用: 稳压器开关
文件页数/大小: 38 页 / 858 K
品牌: FREESCALE [ Freescale ]
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ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS (continued)  
Characteristics noted under conditions -40°C TA 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using  
the typical application circuit (see Figures 33) unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
BOOST REGULATOR  
Boost Regulator MOSFET Maximum ON Time (21)  
Boost Regulator Control Loop Propagation Delay (21)  
t
24  
50  
µs  
ns  
ns  
ON  
t
BST_PD  
Boost Switching Node VBD Rise Time (21)  
IBST = 20 mA  
t
B_RISE  
5.0  
3.0  
Boost Switching Node VBD Fall Time (21)  
IBST = 20 mA  
t
ns  
B_FALL  
LINEAR REGULATOR (LDO)  
Fault Condition Time-Out  
Retry Timer Cycle  
t
7.0  
70  
10  
15  
ms  
ms  
FAULT  
t
100  
150  
Ret  
RESET MONITOR (RST)  
Monitoring LFB Pin Delay  
Monitoring INV Pin Delay  
SCA, SCL PIN, I2C BUS (STANDARD)  
t
12  
12  
28  
28  
µs  
µs  
D_RST_LFB  
t
D_RST_INV  
SCL Clock Frequency (21)  
SCL  
f
100  
kHz  
µs  
Bus Free Time Between a STOP and a START Condition (21)  
BUF  
t
4.7  
Hold Time (Repeated) START Condition (After this period, the first clock  
pulse is generated.) (21)  
t
µs  
HD-STA  
4.0  
4.7  
4.0  
Low Period of the SCL Clock (21)  
High Period of the SCL Clock (21)  
LOW  
t
µs  
µs  
ns  
t
HIGH  
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400  
pF, 3.0 mA Sink Current (21), (23)  
t
F
250  
Setup Time for a Repeated START Condition (21)  
SU-STA  
t
4.7  
0.0  
250  
4.0  
µs  
µs  
ns  
µs  
pF  
(22)  
Data Hold Time for I2C Bus Devices (21)  
Data Setup Time (21)  
,
HD-DAT  
T
t
t
SU-DA  
Setup Time for STOP Condition (21)  
SU-STO  
CB  
t
Capacitive Load for Each Bus Line (21)  
400  
Notes  
21. Design information only. This parameter is not production tested.  
22. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the  
undefined region of the falling edge of SCL.  
23. VIH is High Level Voltage on I2C bus lines and VIL is Low Level Voltage on I2C bus lines  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
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