ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
33981
THERMAL ADDENDUM (REV 2.0)
INTRODUCTION
This thermal addendum is provided as a supplement to the 33981 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
16-PIN
PQFN
PACKAGING AND THERMAL CONSIDERATIONS
This package is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures,
TJ1 and TJ2, and a thermal resistance matrix with RθJAmn
.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
PNA SUFFIX
98ARL10521D
16-PIN PQFN
12 MM X 12 MM
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RθJ21 and RθJ22, respectively.
Note For package dimensions, refer to
the 33981 device datasheet.
RθJA11 RθJA12
RθJA21 RθJA22
TJ1
TJ2
P1
P2
.
=
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
STANDARDS
Table 7. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Resistance
(1), (2)
Ρ
Ρ
Ρ
Ρ
22
7.0
62
18
4.0
48
41
27
81
1.0
θJAmn
0.2 mm spacing
between PCB pads
(2), (3)
θJBmn
(1), (4)
θJAmn
(5)
<1.0
0.0
θJCmn
Notes
0.2 mm spacing
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
between PCB pads
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Figure 44. Surface mount for power PQFN
with exposed pads
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FREESCALE [ Freescale ]
