FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
RST Wake-up
To disable the watchdog function in Normal Mode the user
must connect the WDCONF pin to ground. This measure
effectively disables Normal Request Mode. The WDOFF bit
in the Watchdog Status Register (WDSR) will be set. This
condition is only detected during Reset Mode.
While in Stop Mode, the 33912 can wake-up when the
RST pin is held low long enough to pass the internal glitch
filter. Then, the 33912 will change to Normal Request or
Normal Modes depending on the WDCONF pin
configuration. The RST wake-up does not generate an
interrupt and is not reported via SPI.
If neither a resistor nor a connection to ground is detected,
the watchdog falls back to the internal lower precision
timebase of 150ms (typ.) and signals the faulty condition
through the Watchdog Status Register (WDSR).
From Stop Mode, the following wake-up events can be
configured:
The watchdog timebase can be further divided by a
prescaler which can be configured by the Timing Control
Register (TIMCR). During Normal Request Mode, the
window watchdog is not active but there is a 150ms (typ.)
timeout for leaving the Normal Request Mode. In case of a
timeout, the 33912 will enter into Reset Mode, resetting the
microcontroller before entering again into Normal Request
Mode.
• Wake-up from Lx inputs without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
• CS wake-up
• LIN wake-up
• RST wake-up
From Sleep Mode, the following wake-up events can be
configured:
HIGH SIDE OUTPUT PINS HS1 AND HS2
• Wake-up from Lx inputs without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
These outputs are two high side drivers intended to drive
small resistive loads or LEDs incorporating the following
features:
• LIN wake-up
• PWM capability (software maskable)
• Open load detection
WINDOW WATCHDOG
• Current limitation
The 33912 includes a configurable window watchdog
which is active in Normal Mode. The watchdog can be
configured by an external resistor connected to the WDCONF
pin. The resistor is used to achieve higher precision in the
timebase used for the watchdog.
• Over-temperature shutdown (with maskable interrupt)
• High-voltage shutdown (software maskable)
• Cyclic sense
The high side switches are controlled by the bits HS1:2 in
the High Side Control Register (HSCR).
SPI clears are performed by writing through the SPI in the
MOD bits of the Mode Control Register (MCR).
PWM Capability (direct access)
During the first half of the SPI timeout, watchdog clears are
not allowed, but after the first half of the SPI timeout window,
the clear operation opens. If a clear operation is performed
outside the window, the 33912 will reset the MCU, in the
same way as when the watchdog overflows.
Each high side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
If both the bits HS1 and PWMHS1 are set in the High Side
Control Register (HSCR), then the HS1 driver is turned on if
the PWMIN pin is high and turned of if the PWMIN pin is low.
This applies to HS2 configuring HS2 and PWMHS2 bits.
WINDOW CLOSED
NO WATCHDOG CLEAR
ALLOWED
WINDOW OPEN
FOR WATCHDOG
CLEAR
WD TIMING X 50%
WD TIMING X 50%
WD PERIOD (t
)
PWD
WD TIMING SELECTED BY REGISTER
ON WDCONF PIN
Figure 16. Window Watchdog Operation
33912
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FREESCALE [ Freescale ]
