MC33910BAC / MC34910BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
MXx - Analog Multiplexer Input Select
Writing to the interrupt mask register (IMR) will return the
ISR.
These write-only bits selects which analog input is
multiplexed to the ADOUT0 pin according to Table 54.
Table 56. Interrupt Mask Register - $E
When disabled or when in Stop or Sleep mode, the output
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
C3
HSM
1
C2
-.
C1
LINM
1
C0
VMM
1
Write
Table 54. Analog Multiplexer Channel Select
Reset Value
Reset Condition
1
MX2
MX1
MX0
Meaning
POR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
Reserved
HSM - High Side Interrupt Mask
Die Temperature Sensor
VSENSE input
L1 input
This write-only bit enables/disables interrupts generated in
the high side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
Reserved
Reserved
LINM - LIN Interrupts Mask
Reserved
This write-only bit enables/disables interrupts generated in
the LIN block.
Configuration Register - CFR
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
This register controls the cyclic sense timing multiplier.
Table 55. Configuration Register - $D
VMM - Voltage Monitor Interrupt Mask
C3
C2
C1
C0
This write-only bit enables/disables interrupts generated in
the voltage monitor block. The only maskable interrupt in the
voltage monitor block is the VSUP over-voltage interrupt.
Write
0
CYSX8
0
0
Reset
Value
0
0
0
0
1 = Interrupts Enabled
0 = Interrupts Disabled
POR, Reset
mode or
ext_reset
Reset
Condition
POR
POR
POR
Interrupt Source Register - ISR
This register allows the MCU to determine the source of
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
HVDD - Hall Sensor Supply Enable
This write-only bit enables/disables the state of the hall
sensor supply.
1 = HVDD on
0 = HVDD off
This register is also returned when writing to the interrupt
mask register (IMR).
CYSX8 - Cyclic Sense Timing x 8
Table 57. Interrupt Source Register - $E/$F
This write-only bit influences the Cyclic Sense period as
shown in Table 51.
S3
S2
S1
S0
1 = Multiplier enabled
0 = None
Read
ISR3
ISR2
ISR1
ISR0
ISRx - Interrupt Source Register
Interrupt Mask Register - IMR
These read-only bits indicate the interrupt source following
Table 58. If no interrupt is pending than all bits are 0.
This register allow to mask some of interrupt sources. The
respective flags within the ISR will continue to work but will
not generate interrupts to the MCU. The 5.0 V Regulator
over-temperature prewarning interrupt and under-voltage
(VSUV) interrupts can not be masked and will always cause
an interrupt.
In case more than one interrupt is pending, than the
interrupt sources are handled sequentially multiplex.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
84
FREESCALE [ Freescale ]
