MC33910BAC / MC34910BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
CYSTx - Cyclic Sense Period Prescaler Select
1 = Last reset caused by watchdog timeout
0 = None
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
configuration register (CFR) (see Configuration Register -
CFR).
WDERR - Watchdog Error
This read-only bit signals the detection of a missing
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The windowing function is
disabled.
This option is only active if the high side switch is enabled
when entering in Stop or Sleep mode. Otherwise a timed
wake-up is performed after the period shown in Table 51.
1 = WDCONF pin resistor missing
Table 51. Cyclic Sense Interval
0 = WDCONF pin resistor not floating
CYSX8(123) CYST2
CYST1
CYST0
Interval
WDOFF - Watchdog Off
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
No Cyclic Sense
20 ms
This read-only bit signals that the watchdog pin connected
to GND and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
40 ms
60 ms
80 ms
100 ms
120 ms
140 ms
160 ms
320 ms
480 ms
640 ms
800 ms
960 ms
1120 ms
1 = Watchdog is disabled
0 = Watchdog is enabled
WDWO - Watchdog Window Open
This read-only bit signals when the watchdog window is
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
1 = Watchdog window open
0 = Watchdog window closed
Analog Multiplexer Control Register - MUXCR
This register controls the analog multiplexer and selects
the divider ration for the L1 input divider.
Notes
123. bit CYSX8 is located in configuration register (CFR)
Table 53. Analog Multiplexer Control Register -$C
Watchdog Status Register
C3
L1DS
1
C2
MX2
0
C1
MX1
0
C0
MX0
0
This register returns the watchdog status information and
is also returned when writing to the TIMCR.
Write
Table 52. Watchdog Status Register - $A/$B
Reset Value
Reset Condition
S3
S2
S1
S0
POR
POR, Reset mode or ext_reset
Read
WDTO
WDERR WDOFF
WDWO
L1DS - L1 Analog Input Divider Select
WDTO - Watchdog Time Out
This write-only bit selects the resistor divider for the L1
analog input. Voltage is internally clamped to VDD.
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
watchdog within the window closed.
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
Any access to this register or the TIMCR will clear the
WDTO bit.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
83
FREESCALE [ Freescale ]
