MC33910G5AC/MC3433910G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Configuration Register - CFR
HSM - High Side Interrupt Mask
This register controls the Hall Sensor Supply enable/
disable and the cyclic sense timing multiplier.
This write-only bit enables/disables interrupts generated in
the high side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
Table 27. Configuration Register - $D
C3
C2
C1
C0
LINM - LIN Interrupts Mask
Write
HVDD
CYSX8
0
0
This write-only bit enables/disables interrupts generated in
the LIN block.
Reset
Value
0
0
0
0
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
POR, Reset
mode or
ext_reset
Reset
Condition
POR
POR
POR
VMM - Voltage Monitor Interrupt Mask
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the VSUP over-voltage interrupt.
HVDD - Hall Sensor Supply Enable
This write-only bit enables/disables the state of the hall
sensor supply.
1 = Interrupts Enabled
0 = Interrupts Disabled
1 = HVDD on
0 = HVDD off
Interrupt Source Register - ISR
CYSX8 - Cyclic Sense Timing x 8.
This register allows the MCU to determine the source of
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
This write-only bit influences the cyclic sense and Forced
Wake-up period as shown in Table 23.
1 = Multiplier enabled
0 = None
Interrupt Mask Register - IMR
This register is also returned when writing to the Interrupt
Mask Register (IMR).
This register allows masking of some of the interrupt
sources. No interrupt will be generated to the MCU and no
flag will be set in the ISR register. The 5.0V Regulator over-
temperature prewarning interrupt and Under-voltage (VSUV)
interrupts can not be masked and will always cause an
interrupt.
Table 29. Interrupt Source Register - $E/$F
S3
S2
S1
S0
Read
ISR3
ISR2
ISR1
ISR0
Writing to the IMR will return the ISR.
ISRx - Interrupt Source Register
Table 28. Interrupt Mask Register - $E
These read-only bits indicate the interrupt source following
Table 30. If no interrupt is pending then all bits are 0.
C3
C2
C1
C0
In case more than one interrupt is pending, the interrupt
sources are handled sequentially multiplex.
Write
HSM
0
LINM
VMM
Reset
Value
1
1
1
1
Reset
Condition
POR
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
44
FREESCALE [ Freescale ]
