MC33910G5AC/MC3433910G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
Table 23. Cyclic Sense and Force Wake-up Interval
CYSX8(66) CYST2
CYST1
CYST0
Interval
1 = Watchdog is disabled
0 = Watchdog is enabled
X
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
No cyclic sense(67)
20 ms
0
0
40 ms
WDWO - Watchdog Window Open
0
60 ms
This read-only bit signals when the watchdog window is
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
0
80 ms
0
100 ms
120 ms
140 ms
160 ms
320 ms
480 ms
640 ms
800 ms
960 ms
1120 ms
1 = Watchdog window open
0 = Watchdog window closed
0
0
1
Analog Multiplexer Control Register - MUXCR
1
This register controls the analog multiplexer and selects
the divider ration for the L1 input divider.
1
1
Table 25. Analog Multiplexer Control Register -$C
1
1
1
C3
C2
C1
C0
Write
L1DS
MX2
MX1
MX0
Notes
Reset
Value
66. bit CYSX8 is located in Configuration Register (CFR)
67. No Cyclic Sense and no Force Wake-up available.
1
0
0
0
Reset
Condition
POR
POR, Reset mode or ext_reset
Watchdog Status Register - WDSR
This register returns the Watchdog status information and
is also returned when writing to the TIMCR.
L1DS - L1 Analog Input Divider Select
This write-only bit selects the resistor divider for the L1
analog input. Voltage is internally clamped to VDD.
Table 24. Watchdog Status Register - $A/$B
S3
S2
S1
S0
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
Read
WDTO
WDERR WDOFF
WDWO
MXx - Analog Multiplexer Input Select
WDTO - Watchdog Timeout
These write-only bits selects which analog input is
multiplexed to the ADOUT0 pin according to Table 26.
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
When disabled or when in Stop or Sleep mode, the output
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
Any access to this register or the Timing Control Register
(TIMCR) will clear the WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None
Table 26. Analog Multiplexer Channel Select
MX2
MX1
MX0
Meaning
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
Reserved
WDERR - Watchdog Error
This read-only bit signals the detection of a missing
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The Windowing function is
disabled.
Die Temperature Sensor
VSENSE input
L1 input
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
Reserved
Reserved
Reserved
WDOFF - Watchdog Off
This read-only bit signals that the watchdog pin connected
to Ground and therefore disabled. In this case watchdog
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
FREESCALE [ Freescale ]
