MC33910G5AC/MC3433910G5AC
0 = Normal
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
High Side Control Register - HSCR
This register controls the operation of the high side drivers.
Writing to this register returns the High Side Status Register
(HSSR).
Timing Control Register - TIMCR
This register allows to configure the watchdog, the cyclic
sense and Forced Wake-up periods. Writing to the Timing
Control Register (TIMCR) will also return the Watchdog
Status Register (WDSR).
Table 19. High Side Control Register - $6
C3
C2
C1
C0
Table 21. Timing Control Register - $A
Write
PWMHS2 PWMHS1
HS2
HS1
C3
C2
C1
C0
Reset
Value
0
0
0
0
WD2
WD1
WD0
Write
CS/WD
Reset
Condition
POR, Reset mode, ext_reset, HSx
over-temp or (VSOV & HVSE)
POR
CYST2
CYST1
CYST0
Reset
Value
-
-
0
0
0
PWMHSx - PWM Input Control Enable.
This write-only bit enables/disables the PWMIN input pin
to control the respective high side switch. The corresponding
high side switch must be enabled (HSx bit).
Reset
Condition
POR
1 = PWMIN input controls HSx output.
0 = HSx is controlled only by SPI.
CS/WD - Cyclic Sense or Watchdog prescaler select
This write-only bit selects which prescaler is being written
to, the Cyclic Sense/Forced Wake-up prescaler or the
Watchdog prescaler.
HSx - HSx Switch Control.
This write-only bit enables/disables the corresponding
high side switch.
1 = Cyclic Sense/Forced Wake-up Prescaler selected
0 = Watchdog Prescaler select
1 = HSx switch on.
0 = HSx switch off.
WDx - Watchdog Prescaler
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 22. This configuration is valid only if
windowing watchdog is active.
High Side Status Register - HSSR
This register returns the status of the high side switches
and is also returned when writing to the HSCR.
Table 22. Watchdog Prescaler
Table 20. High Side Status Register - $6/$7
WD2
WD1
WD0
Prescaler Divider
S3
S2
S1
S0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
Read
HS2OP
HS2CL
HS1OP
HS1CL
4
High Side thermal shutdown
6
A thermal shutdown of the high side drivers is indicated by
setting all HSxOP and HSxCL bits simultaneously.
8
10
12
14
HSxOP - High Side Switch Open-Load Detection
This read-only bit signals that the high side switches are
conducting current below a certain threshold indicating
possible load disconnection.
CYSTx - Cyclic Sense Period Prescaler Select
1 = HSx Open Load detected (or thermal shutdown)
0 = Normal
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 44).
HSxCL - High Side Current Limitation
This option is only active if one of the high side switches is
enabled when entering in Stop or Sleep mode. Otherwise, a
timed wake-up is performed after the period shown in
Table 23.
This read-only bit indicates that the respective high side
switch is operating in current limitation mode.
1 = HSx in current limitation (or thermal shutdown)
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
FREESCALE [ Freescale ]
