FUNCTIONAL DESCRIPTION
DEVICE OPERATION
DEVICE OPERATION
SPI INTEGRITY CHECK
POWER SUPPLY
The 33879 device has been designed with ultra-low Sleep
mode currents. The device may enter Sleep mode via the EN
pin or the VDD pin. In the Sleep mode (EN or VDD ≤ 0.8 V),
the current consumed by the VPWR pin is less than 5.0 μA.
Checking the integrity of the SPI communication with the
initial power-up of the VDD and EN pins is recommended.
After initial system start-up or reset, the MCU will write one
32-bit pattern to the 33879. The first 16 bits read by the MCU
will be 8 logic [0]s followed by the fault status of the outputs.
The second 16 bits will be the same bit pattern sent by the
MCU. By the MCU receiving the same bit pattern it sent, bus
integrity is confirmed. Please note the second 16-bit pattern
the MCU sends to the device is the command word and will
be transferred to the outputs with rising edge of CS.
Placing the 33879 in Sleep mode resets the internal
registers to the Power-ON Reset state. The reset state is
defined as all outputs off and Open Load Detection Current
disabled.
To place the 33879 in the Sleep mode, either command all
outputs off and apply logic low to the EN input pin or remove
power from the VDD supply pin. Prior to removing VDD from
the device, it is recommended that all control inputs from the
MCU be low.
Important A SCLK pulse count strategy has been
implemented to ensure integrity of SPI communications. SPI
messages consisting of 16 SCLK pulses and multiples of
8 clock pulses thereafter will be acknowledged. SPI
messages consisting of other than 16 + multiples of 8 SCLK
pulses will be ignored by the device.
PARALLELING OF OUTPUTS
Using MOSFETs as an output switch conveniently allows
the paralleling of outputs for increased current capability.
RDS(ON) of MOSFETs have an inherent positive temperature
coefficient that provides balanced current sharing between
outputs without destructive operation. This mode of operation
may be desirable in the event the application requires lower
power dissipation or the added capability of switching higher
currents. Performance of parallel operation results in a
corresponding decrease in RDS(ON) while the output OFF
Open Load Detection Currents and the output current limits
increase correspondingly. Paralleling outputs from two or
more different IC devices is possible but not recommended.
OVER-TEMPERATURE FAULT
Over-temperature detection and shutdown circuits are
specifically incorporated for each individual output. The
shutdown following an over-temperature condition is
independent of the system clock or any other logic signal.
Each independent output shuts down at 155°C to 185°C.
When an output shuts down owing to an over-temperature
fault, no other outputs are affected. The MCU recognizes the
fault by a one in the fault status register. After the 33879
device has cooled below the switch point temperature and
15°C hysteresis, the output will activate unless told otherwise
by the MCU via SPI to shut down.
FAULT LOGIC OPERATION
Fault logic of the 33879 device has been greatly simplified
over other devices using SPI communications. As command
word one is being written into the shift register, a fault status
word is being simultaneously written out and received by the
MCU. Regardless of the configuration, with no outputs
faulted and Open Load Detection Current enabled, all status
bits being received by the MCU will be zero. When outputs
are faulted (off state open circuit or on state short-circuit/
over-temperature), the status bits being received by the MCU
will be one. The distinction between open circuit fault and
short/over-temperature is completed via the command word.
For example, when a zero command bit is sent and a one
fault is received in the following word, the fault is open/short-
to-battery for high side drive or open/short-to-ground for low
side drive. In the same manner, when a one command bit is
sent and a one fault is received in the following word, the fault
is a short-to-ground/over-temperature for high side drive or
short-to-battery/over-temperature for low side drive. The
timing between two write words must be greater than 300 μs
to allow adequate time to sense and report the proper fault
status.
OVER-VOLTAGE FAULT
An over-voltage condition on the VPWR pin will cause the
device to shut down all outputs until the over-voltage
condition is removed. When the over-voltage condition is
removed, the outputs will resume their previous state. This
device does not detect an over-voltage on the VDD pin. The
over-voltage threshold on the VPWR pin is specified as
VPWR(OV) V, with 1.0 V typical hysteresis. A VPWR over-
voltage detection is global, causing all outputs to be turned
OFF.
OUTPUT OFF OPEN LOAD FAULT
An output OFF open load fault is the detection and
reporting of an open load when the corresponding output is
disabled (input bit programmed to a logic low state). The
Output OFF Open Load fault is detected by comparing the
drain-to-source voltage of the specific MOSFET output to an
internally generated reference. Each output has one
dedicated comparator for this purpose.
An output OFF open load fault is indicated when the drain-
to-source voltage is less than the output threshold voltage
(VOUT(FLT-TH)) of 2.5 V to 4.0 V. Hence, the 33879 will
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FREESCALE [ Freescale ]
