ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING(14)
Recommended Frequency of SPI Operation(14)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
DI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to DI (Required Hold Time)
DI, CS, SCLK Signal Rise Time(15)
fSPI
–
100
50
16
20
–
4.0
–
–
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
LEAD
t
–
–
LAG
t
–
–
DI(SU)
t
–
–
DI(HOLD)
t
t
5.0
5.0
–
–
R(DI)
F(DI)
DI, CS, SCLK Signal Fall Time(15)
–
–
Time from Falling Edge of CS to DO Low-impedance(16)
Time from Rising Edge of CS to DO High-impedance(17)
Time from Rising Edge of SCLK to DO Data Valid(18)
Notes
t
–
55
55
55
DO(EN)
t
–
–
DO(DIS)
t
–
25
VALID
14. This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface.
15. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for output status data to be available for use at DO pin.
17. Time required for output status data to be terminated at DO pin.
18. Time required to obtain valid data out from DO following the rise of SCLK.
TIMING DIAGRAMS
CS
0.2 V
DD
t
t
LAG
LEAD
0.7 V
0.2 V
DD
SCLK
DD
t
t
DI(SU) DI(HOLD)
0.7 V
0.2 V
DD
DI
MSB in
DD
t
t
DO(DIS)
DO(EN)
t
VALID
0.7 V
0.2 V
DD
DO
MSB out
LSB out
DD
Figure 4. SPI Timing Diagram
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
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