FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
described in Table 9, page 22. The SI input has an active
the CS pin is put into a logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes state on
the rising edge of SCLK and reads out on the falling edge of
SCLK. Fault and input status descriptions are provided in
Table 16, page 26.
internal pull-down, IDWN
.
DIGITAL DRAIN VOLTAGE (VDD)
This pin is an external voltage input pin used to supply
power to the SPI circuit. In the event VDD is lost, an internal
supply provides power to a portion of the logic, ensuring
limited functionality of the device.
HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2)
Protected 35mΩ high side power output pins to the load.
GROUND (GND)
FAIL-SAFE INPUT (FSI)
This pin is the ground for the device.
The value of the resistance connected between this pin
and ground determines the state of the outputs after a
watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF or the output HSO only is
ON. If the FSI pin is left to float up to a logic [1] level, then the
outputs HS0 and HS2 will turn ON when in the Fail-safe state.
When the FSI pin is connected to GND, the watchdog circuit
and Fail-safe operation are disabled. This pin incorporates an
active internal pull-up current source.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the
source of operational power for the device. The VPWR contact
is the backside surface mount tab of the package.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high-impedance state until
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FREESCALE [ Freescale ]
