INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR, VDD
VPWR
VDD
GND
POR
80µA
Sleep PWR
Oscillator
Bandgap
VCAL
V
CCD2_OUT
CCD1_OUT
DD
15µA
CCD2 Outputs
CCD1 Outputs
15µA
CCD2_REC
CCD1_REC
DEFAULT
EN
53V
100K
Gate Control
Open/Short
40µA
P1
P3
P5
P7
SI
+
–
R
15µA
15µA
15µA
15µA
15µA
S
CCGND
CCGND
lLimit
Outputs 1 to 8
OUT 1
75µA
53V
to
Gate Control
Open/Short
OUT 8
Logic Control &
SPI Interface
+
–
R
S
PGND
PGND
PGND
V
lLimit
DD
15µA
Predriver1,2,3
CS
SCLK
SO
VDSNS1
V
PWR
PWM1
Gate Drive
Control &
Diagnostics
GD1
15µA
PWM2
PWM3
PWM4
PWM5
PWM6
VSSNS123
15µA
15µA
15µA
15µA
15µA
Predriver4,5,6
VDSNS4
V
PWR
Gate Drive
Control &
Diagnostics
GD4
VSSNS456
Differential
Amplifier
+
−
+
−
LRFDBK
REXT
+
−
VCAL
+
−
VCAL
RI_REF
Exposed
Pad
Figure 2. 33800 Simplified Internal Block Diagram
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
FREESCALE [ Freescale ]
