33781 参数 Datasheet PDF下载

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75V

≤

V

CC

≤

5.25V, 9.0V

≤

V

SUPn

≤

25V,-40°C

≤

T

A

≤

90°C,

unless otherwise

noted. Voltages relative to GND, unless otherwise noted. Typical values noted reflect the approximate mean values of the

parameter at T

A

= 25°C under nominal conditions, unless otherwise noted.

Characteristic

BUS TRANSMITTER (DnH, DnL)

Output Bus Idle Voltage (Drop)

I

nH

= -200mA, I

nL

= 200mA

Output Signal High Voltage (Differential)

-12.5mA

≤

InH

≤

1.0mA, -1.0mA

≤

InL

≤

12.5mA

Output Signal Low Voltage (Differential)

-12.5mA

≤

InH

≤

1.0mA, -1.0mA

≤

InL

≤

12.5mA

Symbol

Min

Typ

Max

Unit

V

DnD(Drop)

–

V

DnD(HIGH)

4.175

V

DnD(LOW)

1.175

V

MID

V

CMP

V

MIDPP(IDLE)

V

SUPn

/

2 - 0.8

0

–

1.5

V

SUPn

/2

–

–

1.825

V

SUPn

/

2 +0.8

30

300

4.5

4.825

–

1.6

V

V

V

Vmid, (DnH + DnL)/2 (Voltage Halfway Between Bus High Side and

Bus Low Side

VCM Peak to Peak (Maximum Vmid-Minimum Vmid)

For Vmid (Idle), Vmid (Signal_H), Vmid

For Signal to Idle, Idle, Idle to Signal,

VmidPP(Idle)=Vmid(Max)- Vmid (Min)

Bus Driver Vmid Peak to Peak (Dnh+DnL)/2

For Signal_H to Signal_L, Signal_L, Signal_L to Signal_H, Signal_H

VmidPP(Signal)=Vmid(Max)-Vmid(Min)

Output High Side (DnH) Driver Current Limit

Fault Condition: DnH = 0V

Normal Operation

Fault Condition: DnH = V

SUPn

Output Low Side (DnL) Driver Current Limit

Fault Condition: DnL = 0V

Fault Condition: DnL = V

SUPn

Signal mode Over-current Shutdown

l ISSD l DnH, DnL

Disabled High Side (DnH) Bus Leakage (DnL open)

DnH = 0V

DnH = V

SUPn

Disabled Low Side (DnL) Bus Leakage (DnH open)

DnL = 0V

DnL = V

SUPn

(Signal_L)

Bus Driver Vmid Peak to Peak, (DnH+DnL)/2

V

mV

mV

V

MIDPP(SIGNAL)

–

–

80

mV

I

CL(HIGH)

-600

-400

150

I

CL(LOW)

-350

200

I

SSD

I

LK(HIGH)

-1.0

-1.0

I

LK(LOW)

-1.0

-1.0

–

–

1.0

1.0

–

–

1.0

1.0

20

–

–

-150

400

60

–

–

–

-200

-200

350

mA

mA

mA

mA

mA

Notes

5. Not measured in production.

6. InH=bus current at DnH, InL=bus current at DnL

7. V

DnD

=V

DnH

-V

DnL

8. Max V

DnD

= VSUPn - 2 * V

MID_OFFSET

- V

DnD(Drop)

, V

MID_OFFSET

= |V

MID

- V

SUPn

/ 2|

9.

Worst Case Disabled Low Side Bus Leakage for DnL occurs with DnL = V

SUP

and DnH = 0V. In this configuration, the DnL leakage

current can exceed 1mA. This is not measured in production.

33781

Analog Integrated Circuit Device Data

Freescale Semiconductor

7