ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75V ≤ VCC ≤ 5.25V, 9.0V ≤ VSUPn ≤ 25V,-40°C ≤ TA ≤ 90°C, unless otherwise
noted. Voltages relative to GND, unless otherwise noted. Typical values noted reflect the approximate mean values of the
parameter at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
BUS TRANSMITTER
Idle-to-Signal and Signal-to-Idle Slew Rate(13)
t
3.0
3.0
6.0
6.0
8.0
8.0
V/μs
V/μs
SLEW(IDLE)
Signal High-to-Low and Signal Low-to-High Slew
Rate(13),(14) (See Data Valid DSIS to DnD Timing)
t
SLEW(SIGNAL)
Communication Data Rate Capability(14) (Ensured by
Transmitter Data
D
77.1
–
200
kbps
RATE
Valid and Receiver Delay Measurements)
Data Rate(before frequency spreading)
(14)
Signal Bit Time (1 / D
)
t
5.0
–
–
–
μs
μs
RATE
BIT
The Max value depends on the settings in the FSEL bits
DBUS Start Delay, CS0 Rising Edge to DBUS(14)
note: DLY is the inter-message delay selected in the
DnCTRL register
t
2/3tBIT + (DLY-2) * t
5/3tBIT + (DLY-2) *
DBUSSTART2
BIT
t
BIT
Data Valid(13)
μs
DSIF = 0.5 * V to DnD Fall = 5.5 V (9V < V
< 40V)
t
–
–
–
–
–
–
–
–
5.3
1.0
1.0
1.0
CC
SUPn
SUPn
SUPn
SUPn
DVLD1
DSIS = 0.5 * V
to DnD Fall = 2.8V (9V < V
< 40V)
< 40V)
< 40V)
t
CC
DVLD2
t
DSIS = 0.5 * V to DnD Rise = 3.2V (9V < V
CC
DVLD3
t
DSIF = 0.5 * V to DnD Rise = 6.5 V (9V < V
CC
DVLD4
Signal mode Over-current Shutdown Delay(14)
t
3.0
5.0
7.0
μs
μs
OC
Signal Low Time for Logic Zero
33.3% Duty Cycle
t0LO
0.6 * t
BIT
2/3 *
0.73 * t
BIT
BIT
t
(2/3*tBIT) + 10% for threshold delta
BIT
Signal Low Time for Logic One
66.7% Duty Cycle
t1LO
0.3 * t
BIT
1/3 *
0.37 * t
μs
t
(1/3*tBIT) + 10% for threshold delta
BIT
Notes
13. C = 2.8nF from DnH to DnL and 2.2nF from DnH and DnL to GND, capacitor tolerance = ±10%.
14. Not measured in production.
33781
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
FREESCALE [ Freescale ]
