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33742S 参数 Datasheet PDF下载

33742S图片预览
型号: 33742S
PDF下载: 下载PDF文件 查看货源
内容描述: 系统基础芯片( SBC)与增强型高速CAN收发器 [System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver]
分类和应用:
文件页数/大小: 65 页 / 1605 K
品牌: FREESCALE [ Freescale ]
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TYPICAL APPLICATIONS  
POWER-UP AND VDD GOING LOW WITH SLEEP MODE AS DEFAULT LOW POWER MODE IS SELECTED  
The first part of Figure 35 is identical to Figure 34. If VDD is pulled below the VDD under voltage reset (typ 4.6V), say by an  
overcurrent or short circuit (for instance, short to 4.0 V), and if the low power mode previously selected was Sleep mode and if  
the BATFAIL flag has been cleared, the 33742 enters in Reset mode for a time period of 100 ms. The WDOG pin stays HIGH,  
but the high level (Voh) follows VDD level. The RST and INT pins are low. After 100 ms the 33742 goes into Sleep mode, and  
the VDD and V2 are off.  
Figure 35 shows an example wherein VDD is shorted to 4.0 V, and after 100 ms the 33742 enters Sleep mode.  
.
Under voltage at VDD  
VDD  
Watchdog refresh  
SPI (CS)  
100 ms  
WD  
RST  
INT  
SBC in Sleep mode  
SBC in Normal request  
& reset modes  
SBC in Normal  
mode  
SBC in  
RESET  
mode  
SBC in Reset mode for  
100ms, then enter  
Sleep mode  
Reset each 350 ms  
Figure 35. Undervoltage at VDD. Sleep mode selected.  
CANH  
CANH (33742)  
CANL (33742)  
CANH (33742)  
CANH  
R6  
R7  
CH  
CL  
CH  
R5  
CANL  
CANL (33742)  
CANL  
CAN Connector  
CS  
CL  
CAN Connector  
Legend  
Legend  
R5: 60 Ω  
CL, CH: 220 pF  
R6, R7: 30 Ω  
CL, CH: 220 pF  
CS: > 470 pF  
Figure 37. CAN Bus Split Termination  
Figure 36. CAN Bus Standard Termination  
33742  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
55  
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