ELECTRICAL CHARACTERISTICS
STATIC
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, f
CLK
= 176.4 kHz unless
otherwise noted. Typical values noted reflect the approximate parameter means at T
A
= 27°C under nominal conditions unless
otherwise noted.
Characteristic
Switching Power Supply 2
VOUT2 Output Voltage (I
o
= 0~80 mA)
HG Output Voltage
(I
source
= 400
µA)
(I
sink
= 400
µA)
LG Output Voltage
(I
source
= 400
µA)
(I
sink
= 400
µA)
Series Pass Power Supply Circuit
SREG1 Control Voltage (I
o
= 5~60 mA)
SREG1-Error AMP Input offset voltage
SREG2 Control Voltage (I
o
= 6~80 mA)
SREG2-Error AMP Input offset voltage
SREG3 Control Voltage (I
o
= 5~60 mA)
SREG3-Error AMP Input offset voltage
SREG2G Output Voltage
(I
sink
= 2.5
µA)
Power Switch On Resistance
VOUT1 Circuit
VOUT2 Circuit
VGATE Power Supply Circuit
(I
o
= 0~6 mA)
(I
o
= 0~6 mA)
CH_PUMP Output Voltage (I
source
= 2.5 mA)
(I
sink
= 2.5 mA)
VGH Voltage (Certified value)
V_STDBY Output Voltage for Li_ion (I
o
= 300
µA)
V
GATE_00
V
GATE_10
V
O1_SENSE1LH
V
O1_SENSE_1LL
V
GH
V
LVB
5.5
4.6
VB x 0.85
0
-
1.75
6.0
5.0
-
-
-
-
6.5
5.4
VB
0.4
10.5
2.45
V
R
VOUT1
R
VOUT2
-
-
0.4
0.4
0.6
0.6
V
W
Symbol
Min
Typ
Max
Unit
V
V
OUT2
V
DW2TH
V
DW2TL
V
DW2BH
V
DW2BL
1.05
5.2
0
5.2
0
1.15
-
-
-
-
1.25
VGATE
0.3
VGATE
0.3
V
SREG1
SR1OFST
V
SREG2
SR2OFST
V
SREG3
SR3OFST
SREG2GH
SREG2GL
2.7
-13.5
2.7
-17
2.7
-11
5.0
0
2.8
-
2.8
-
2.8
-
-
-
2.9
24.5
2.9
17
2.9
23
VGATE
0.5
V
mV
V
mV
V
mV
V
V
(I
source
= 2.5
µA)
Notes
11. Connect a transistor with gate capacity of 200 pF or smaller to HG and LG
12. If a capacitor with capacitance of 22 µF is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC
when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is
connected as follows:
SREGI1 = 3.0 V to 3.3 V, 65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND.
SREGI2 = 3.0 V to 3.3 V, 54.46KΩ between SREGO2 and SREGC2, 45.54KΩ between SREGC2 and GND.
SREGI3 = 3.0 V to 3.3 V, 73.84KΩ between SREGO3 and SREGC3, 26.16KΩ between SREGC3 and GND.
13. Calculated by the right formula for input offset: SR1OFST = (Vref x 0.77) - (SREGO1
÷
(100k
÷
34.86k))
14. Calculated by the right formula for input offset: SR2OFST = (Vref x 1) - (SREGO1
÷
(100k
÷
45.54k))
15. Calculated by the right formula for input offset: SR3OFST = (Vref x 0.58) - (SREGO1
÷
(100k
÷
26.16k))
16. Connect a transistor with gate capacity of 300 pF or smaller to REG2G.
17. When VGATESEL1 is Low and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification.
18. When VGATESEL1 is High and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification.
19. When HVB is 4.2 V and the load from V_STDBY is 0.5
µA
or higher.
18730
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
