欢迎访问ic37.com |
会员登录 免费注册
发布采购

18730_06 参数 Datasheet PDF下载

18730_06图片预览
型号: 18730_06
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理IC与五稳压输出编程通过3线串行接口 [Power Management IC with Five Regulated Outputs Programmed Through 3 Wire Serial Interface]
分类和应用:
文件页数/大小: 35 页 / 1054 K
品牌: FREESCALE [ Freescale ]
 浏览型号18730_06的Datasheet PDF文件第13页浏览型号18730_06的Datasheet PDF文件第14页浏览型号18730_06的Datasheet PDF文件第15页浏览型号18730_06的Datasheet PDF文件第16页浏览型号18730_06的Datasheet PDF文件第18页浏览型号18730_06的Datasheet PDF文件第19页浏览型号18730_06的Datasheet PDF文件第20页浏览型号18730_06的Datasheet PDF文件第21页  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
If SLEEP goes High to place the chip into the standby  
mode while any of the WAKEB pins is Low, the chip can be  
awakened again. This may happen if, when an WAKEB pin  
and LSWO are connected, SLEEP goes High earlier than the  
period of time (*1) specified by the external component of the  
WAKEB pin.  
START-UP CONTROL INPUT (SYSTEM CONTROL)  
The latch is set at the rising edge of any WAKE1B-4B input  
pin, and WAKE(int) goes High. WAKE1~4B inputs consist of  
OR logic. At this time, the input pin which went Low keeps  
latched until CLEAR goes High. After the latch is reset by  
CLEAR, WAKE(int) goes Low when SLEEP goes High. The  
latch is also cleared and WAKE(int) goes Low when SLEEP  
goes High before the latch is cleared by CLEAR. In this case,  
CLEAR keeps negated while PGOOD1, 2(Ext) is Low.  
SLEEP keeps negated while PGOOD1, 2(Ext) is Low or  
CLEAR is High. The period of time for which CLEAR and  
SLEEP are negated can be set by the SEQ_SELECT pin.  
Refer to Truth Table 5, on page 12 for the correspondence  
between the SEQ_SELECT pin settings and negation period.  
Also, if the period of time after WAKE(int) goes High until  
CLEAR goes High from Low is longer than the time specified  
by WATCHDOG, internal sleep will start up to place the chip  
into the standby mode.  
(*1: It is 30 µsec when a capacitor is not connected as the  
external component.)  
WAKEB  
CLEAR  
Time specified by WATCHDOG  
WATCHDOG  
WAKE(Int)  
Figure 6. Start-Up Timing Diagram  
STANDBY POWER SUPPLY CIRCUIT  
LSWO  
Short-circuit VBATT and LVB, and connect a  
Schottky diode between VBATT and V_STDBY  
only when using Ni_mh.  
CLEAR  
VBATT  
VO1_SENSE  
VBATT  
LVB  
HVB  
Standby  
Power  
Supply  
Control  
PGOOD1  
PGOOD1(Int)  
V_STDBY  
When using Li_ion, leave LVB open, and short-  
circuit HVB and VBATT.  
V_STDBY  
Figure 7. Standby Power Supply Circuit Diagram  
When PGOOD1(int) is Low, output LVB voltage to  
V_STDBY pin. When PGOOD1(int) is High, output  
VO1_SENSE voltage to V_STDBY pin. When CLEAR is Low,  
LSWO is open. When PGOOD1(int) is High and CLEAR is  
High, LSWO output voltage turns GND. When PGOOD1(int)  
is Low and PGOOD1 is High, discharge the external  
18730  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
17  
 复制成功!