PCI
1
Table 45. PCI AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
PORESET to REQ64 hold time
tPCRHRX
0
50
ns
6
Notes:
1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
description of M66EN.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The setup and hold time is with respect to the rising edge of PORESET.
Table 46 provides the PCI AC timing specifications at 33 MHz.
Table 46. PCI AC Timing Specifications at 33 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
Clock to output valid
t
—
2
11
—
14
—
—
—
50
ns
ns
2
2
PCKHOV
Output hold from clock
Clock to output high impedance
Input setup to clock
tPCKHOX
tPCKHOZ
tPCIVKH
tPCIXKH
tPCRVRH
tPCRHRX
—
3.0
0
ns
2, 3
2, 4
2, 4
5
ns
Input hold from clock
ns
REQ64 to PORESET setup time
PORESET to REQ64 hold time
Notes:
5
clocks
ns
0
5
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The setup and hold time is with respect to the rising edge of PORESET.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
48
Freescale Semiconductor
FREESCALE [ Freescale ]
