JTAG
Figure 30 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Output Data Valid
Data Outputs
VM = Midpoint Voltage (OV /2)
DD
Figure 30. Boundary-Scan Timing Diagram
Figure 31 provides the test access port timing diagram.
JTAG
External Clock
VM
VM
tJTIVKH
tJTIXKH
Input
TDI, TMS
TDO
Data Valid
tJTKLOV
tJTKLOX
Output Data Valid
tJTKLOZ
Output Data Valid
TDO
VM = Midpoint Voltage (OV /2)
DD
Figure 31. Test Access Port Timing Diagram
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
44